Easyi3C is a leading supplier of embedded system tools that simplify the development and debugging of various communication protocols. The company offers a range of products designed to help engineers and developers use I3C/I2C , USB and MIPI, JEDEC, MCTP and other protocols more efficiently.
Because the I3C/I2C bus can connect to a variety of device technologies (CMOS, NMOS, bipolar), the logic '0' (low) and '1' (high) levels are not fixed but depend on the VDD level. VIL refers to the input low voltage, and VIH refers to the input high voltage. Typically, the input reference levels are set to: VIL = 0.3VDD, and VIH = 0.7VDD. Some older devices have fixed input levels of VIL = 1.5V and VIH = 3.0V, but all new devices require this specification to be 30%/70%.
Therefore, VIL and VIH are important parameters in the I3C/I2C protocol, which directly affect the correctness of communication access. Measuring the VIL and VIH of the chip is an important requirement.
With the above theoretical preparation, we know the importance of VIL and VIH testing requirements. Based on the test environment built by our Tower I3C Host Adapter, we can test these two parameters more conveniently to verify whether the chip design meets the requirements.
The first step is to connect the Tower I3C Host Adapter and the test chip as shown below, and add an adjustable resistor R1 and a fixed resistor R2 (1.5KΩ):
The second step is to adjust resistor R1 to 0 and leave R2 floating, which is equivalent to temporarily disconnecting the resistor. Then test the connectivity of the experimental environment to ensure that the chip device can be accessed normally. Perform normal reading and writing through the Tower I3C Host Adapter GUI program Tower console and capture the waveform to ensure that the oscilloscope at the test point is connected properly:
In the third step, after verifying the correct test environment, we connected resistor R2 and continuously adjusted the resistance of R1. Each time we adjusted the resistance of R1, we read the bus waveform using the GUI Tower Console. The following waveforms were obtained for three different R1 resistance values:
(1) Variable resistors R1 = 0Ω, R2 = 1.5KΩ
(2) Variable resistors R1 = 200Ω, R2 = 1.5KΩ
Under this condition, the SDA high level is measured to be 550mv.
(3) Continue to increase the resistance of resistor R1, and the measured waveform is as follows:
As you can see from the image above, read and write access failed.
Combining the above (1), (2) and (3), we can get that the VIH of this chip is 550mv.
The first step is to connect the Tower I3C Host Adapter and the test chip as shown below, and add an adjustable resistor R1 and a fixed resistor R2 (1.5KΩ), and connect the DC Bias:
The second step is to adjust resistor R1 to 0 and leave R2 floating, which is equivalent to temporarily disconnecting the resistor. Then test the connectivity of the experimental environment to ensure that the chip device can be accessed normally. Perform normal reading and writing through the Tower I3C Host Adapter GUI program Tower console and capture the waveform to ensure that the oscilloscope at the test point is connected properly:
Step 3: Select appropriate resistance values for R1 and R2, keep them fixed, and then adjust the DC Bias to increase the low-level voltage. Each time you adjust the voltage, perform a read operation through the GUI Tower Console and capture the waveform on the bus until it becomes inaccessible. The last low-level voltage that works is the VIL of the chip.
From the above introduction, we can know that the test environment built based on our Tower I3C Host Adapter can easily test the chip's VIH and VIL, thereby quickly verifying whether the chip design meets SPEC requirements, providing feedback to chip design engineers, improving chip quality, and increasing product competitiveness.
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