Easyi3C is a leading supplier of embedded system tools that simplify the development and debugging of various communication protocols. The company offers a range of products designed to help engineers and developers use I3C/I2C , USB and MIPI, JEDEC, MCTP and other protocols more efficiently.
With the increasing demand for efficient communication in fields such as data centers, the Internet of Things, consumer electronics, and embedded systems, I3C (Improved Inter-Integrated Circuit) bus technology has attracted widespread attention due to its high speed, low power consumption, and flexibility. As a crucial component of this bus technology, the I3C hub chip provides powerful scalability for multi-device communication, becoming an indispensable part of modern electronic systems.
The I3C HUB (Intelligent Interconnect Hub) is an expansion solution for the I3C bus, enabling complex system interconnection requirements by cascading multiple devices. The following are key points:
As a hub for the I3C bus, the I3C HUB supports multi-device connections and signal expansion. Its main functions include:
Multi- device interconnection : Expands the number of bus connections through cascading, supporting simultaneous connection of multiple master and slave devices.
Level conversion : Compatible with different voltage domains to ensure signal transmission across voltages
Hot-swap : Supports hot-swap functionality, improving system maintainability.
Dynamic configuration : Some models support dynamic master port switching, network partitioning, and multi-chip cascading
Protocol compatibility : Mainstream models support I2C, I3C Basic 1.0, and SMBus protocols, enabling seamless integration between traditional devices and high-speed I3C devices.
Transmission characteristics : Data rate up to 12.5MHz, supporting low power consumption and anti-signal attenuation design
Application scenarios : Widely used in server memory expansion, industrial control, IoT device interconnection, and other fields.
Refer to the official Intel specification:
The I3C hub chip, acting as a hub for the I3C bus, can connect multiple I3C devices to form a device network. This connection method not only simplifies the communication structure between devices but also improves the system's scalability and flexibility. Through the I3C hub chip, the CPU can easily communicate and exchange data with each I3C device, enabling centralized management and control of these devices.
The I3C hub is a universal functional and programming model for hub devices. Its motivation is to enable device vendors and suppliers to build compatible devices, facilitate the development of universal firmware/software drivers for seamless collaboration with multiple I3C hub vendors, accelerate the adoption of I3C in PCI-SIG* and EDSFF solutions, and provide a healthy multi-source supply chain for I3C solutions in server platforms. On Intel's new motherboard platforms, the use of an I3C hub is recommended to simplify motherboard design and improve system stability.
With the background information above, it's easier to understand the chip's functional characteristics. Next, we can test the I3C HUB using the Tower I3C Host Adapter.
1) Connect the I3C Host Adapter to the host via USB.
2) Install the official drivers and accompanying software (Easyi3C Tower Console GUI).
3) Connect the I3C HUB Slave device under test to the I3C interface of the adapter.
Since this is a graphical interface, it is relatively simple and easy to use. You can refer to our previous examples for access testing, so we will skip it for now.
Based on the background information in Chapter 1, we know that to automate the testing of the full functionality of an I3C HUB chip, the I3C Host Adapter must at least meet the following requirements:
1) Adjustable I3C/I2C operating voltage
2) Bus speed can be adjusted.
3) Supports GPIO
4) Supports IBI
5) Can freely switch between I3C/I2C Master mode on the same port.
6) Support CCC
7) Support PULL-UP
The API provided by our Tower I3C Host Adapter can perfectly solve the above requirements and meet the full functional requirements of testing this complex chip. The following example code is provided for user reference:
import sys
from ezi3c.api import *
# Notes: You must make modifications based on your actual salve address
slave_addr = 0x70
ez = ez_open()
if not ez:
print("Cannot open Adapter")
sys.exit(-1)
try:
version = ez_get_version(ez)
print("version:{:08X}".format(version))
clk = ez_get_bus_clk_freq(ez)
print("POR Default Clk Freq(100, 1000): {}".format(clk))
clk = ez_set_bus_clk_freq(ez, 1000, 4000)
print("Cur Clk Freq: {}".format(clk))
duty = ez_get_bus_clk_duty(ez)
print("POR Default Clk Duty(50, 50): {}".format(duty))
duty = ez_set_bus_clk_duty(ez, 50, 40)
print("Cur Clk Duty: {}".format(duty))
ret = ez_set_io_voltage(ez, 1.0)
assert ret == 0
print("> RSTDAA ...")
ez_ccc_rstdaa(ez)
print("> i2c write & read ...")
ret = ez_i2c_write(ez, slave_addr, [0x40, 0xa1, 0xa2, 0xa3, 0xa4])
assert ret == E_OK
ret, data = ez_i2c_write_read(ez, slave_addr, 0x40, 4)
assert ret == 0
assert data == (0xa1, 0xa2, 0xa3, 0xa4)
print("> SETAASA ...")
ez_ccc_setaasa(ez)
print("> i3c write & read ...")
ret = ez_i3c_write(ez, slave_addr, [0x40, 0xb1, 0xb2, 0xb3, 0xb4])
assert ret == 0
ret, data = ez_i3c_write_read(ez, slave_addr, 0x40, 4)
assert ret == 0
assert data == (0xb1, 0xb2, 0xb3, 0xb4)
print("> RSTDAA ...")
ez_ccc_rstdaa(ez)
print("> ENTDAA ...")
ez_ccc_entdaa(ez, [0x08])
addr = 0x08
print("> i3c write & read ...")
ret = ez_i3c_write(ez, addr, [0x40, 0xb1, 0xb2, 0xb3, 0xb4])
assert ret == 0
ret, data = ez_i3c_write_read(ez, addr, 0x40, 4)
assert ret == 0
assert data == (0xb1, 0xb2, 0xb3, 0xb4)
print("> i3c write & read with IBI header...")
ret = ez_i3c_write(ez, addr, [0x40, 0xb1, 0xb2, 0xb3, 0xb4], with_ibi_header=True)
assert ret == 0
ret, data = ez_i3c_write_read(ez, addr, 0x40, 4, with_ibi_header=True)
assert ret == 0
assert data == (0xb1, 0xb2, 0xb3, 0xb4)
print("> i3c write & read with Parity error...")
ret = ez_i3c_write(ez, addr, [0x40, 0x0, 0x0, 0x0, 0x0], inject_parity_err=True)
assert ret == 0
ret, data = ez_i3c_write_read(ez, addr, 0x40, 4)
assert ret == 0
assert data == (0xb1, 0xb2, 0xb3, 0xb4)
finally:
ez_close(ez)The I3C hub will be a standard feature on future Intel motherboards. Using an I3C hub simplifies motherboard design, ensuring compatibility with the legacy I2C SMBUS protocol while meeting the evolving requirements of the I3C protocol. This is a key trend in future chip requirements. As mentioned above, using the Tower I3C Host Adapter allows for convenient testing of the full functionality of I3C hub chips, meeting complex chip testing requirements, shortening chip verification time, and accelerating product launch.
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