Easyi3C is a leading supplier of embedded system tools that simplify the development and debugging of various communication protocols. The company offers a range of products designed to help engineers and developers use I3C/I2C , USB and MIPI, JEDEC, MCTP and other protocols more efficiently.

Testing DDR5 SPD HUB EEPROM based on Tower I3C Host Adapter

1. Introduction to SPD HUB EEPROM

As shown in the diagram above, the SPD HUB is a hub device connected to the I2C/I3C bus. Besides the added HUB functionality, it contains 1024 bytes of SPD data. The DDR5 EEPROM is an EEPROM chip in the DDR5 memory module used to store configuration information. Its main functions include recording parameters such as memory capacity, speed, and timings, which the motherboard reads during startup to correctly configure the memory. The following is key information:

1）Core Functions

Storage configuration information: Records parameters such as memory capacity, frequency, and timing (e.g., CL value). The motherboard automatically identifies the memory specifications by reading the SPD chip (Serial Presence Detect).
Supports On-Die ECC: Some DDR5 EEPROM chips integrate On-Die ECC functionality, which can correct internal errors in the chip and improve data reliability.

2）Technical features

High capacity and low power consumption: DDR5 EEPROM chips typically use BGA packaging, support higher densities (such as 8Gb, 16Gb, etc.), and operate at a voltage of 1.1V, which conforms to the low power consumption design trend of DDR5.
Compatibility: Requires working in conjunction with the PMIC (Power Management Chip) of the DDR5 memory module to ensure voltage and timing matching.

3）Application scenarios

Servers and high-performance computing: DDR5 EEPROM chips are widely used in server memory modules (such as RDIMM and LRDIMM) to support large-scale data processing needs.
Consumer-grade devices: Some high-end consumer-grade DDR5 memory (such as AI glasses and high-performance PCs) also use SPD chips with integrated EEPROM to optimize compatibility.

2. Testing DDR5 SPD HUB EEPROM based on Tower I3C Host Adapter

While traditional DDR4 memory already has SPD EEPROM functionality, DDR5 differs significantly from traditional DDR4 EEPROMs. DDR5 introduces the I3C protocol, improving access speed and adding PEC checks, making access more complex. The JEDEC specification for I3C EEPROM read/write format is as follows:

To make it easy for users to use, we have encapsulated the above format into the following API, allowing customers to easily perform EEPROM read and write operations under I2C and I3C:

For more detailed information, please log Easyi3C Visit the official website to download and learn more for free.

Using the APIs provided above, we can build automated test scripts to meet different needs, making it convenient to test various functions. Below is a code example:

import sys
from ezi3c.api import *
from ezi3c.utils import hex_string
from ezi3c import utils

from ddr5 import Spdhub


ez = ez_open()
if not ez:
    print("Cannot open Adapter")
    sys.exit(-1)
clk = ez_set_bus_clk_freq(ez,1000, 4000)
print("Cur Clk Freq: {}".format(clk))
ret = ez_set_io_voltage(ez, 1.0)
assert ret == 0, "Faield to set IO voltage"

spd = Spdhub(ez, hid=0x00)

try:
    ret = spd.ccc_rstdaa()
    assert ret == 0, "Failed to reset DAA: addr:{:02X}".format(spd.addr)

    ret, data = spd.i2c_read_reg(0, 2)
    assert ret == 0 and data == (0x51, 0x18), "Failed to read SPD data: addr:{:02X}".format(spd.addr)
    print("SPD Data: {}".format(hex_string(data)))

    spd.switch_to_i3c(send_ccc=True)
    ret, data = spd.i3c_read_reg(0, 2)
    assert ret == 0 and data == (0x51, 0x18), "Failed to read SPD data in I3C mode: addr:{:02X}".format(spd.addr)

    ret, data = spd.i3c_read_reg(0, 1)
    assert ret == 0 and data == 0x51, "Failed to read SPD data in I3C mode with PEC: addr:{:02X}".format(spd.addr)

    ret = spd.enable_pec(send_ccc=True)
    assert ret == 0

    ret = spd.i3c_write_reg(0, 0x00, inject_pec_err=True)
    ret, data = spd.i3c_read_reg(52)
    assert ret == 0 and data & 0x02 == 0x02

    ret = spd.i3c_write_reg(0, 0, inject_parity_err=True)
    ret, data = spd.i3c_read_reg(52)
    assert ret == 0 and data & 0x01 == 0x01

    spd.ibi_enable()
    spd.ccc_enec_broadcast(0X01)

    # while True:
    slave, data = spd.ibi_get(block=True)
    print("Received IBI: dev:{:02X}, payload:{}".format(slave, utils.hex_string(data)))


finally:
    spd.ccc_rstdaa()
    ez_close(ez)
    print("Adapter closed.")

3. Summaries

Based on our Tower I3C Host Adapter, DDR5 SPD EERPOM can be tested very easily, meeting complex testing needs, building automated testing environments, shortening chip time to market, and improving work efficiency.

Blog